1. Field of the Invention
This invention relates to a semiconductor integrated circuit formed on a semiconductor chip, and more particularly to a construction of flipflops of a semiconductor integrated circuit.
2. Description of the Related Art
Since a plurality of flipflops are used for a counter, a register or a like element on a semiconductor chip, a test for confirmation of operation of the flipflops themselves must be performed. Since a test of each flipflop requires a large circuit scale by a test circuit, a plurality of flipflops are combined to form a shift register for testing and a shifting operation of the shift register is confirmed to effect a test of the component flipflops. Generally, in a semiconductor integrated circuit formed on a semiconductor chip, from the point of view of a designing efficiency, basic circuits such as flipflops which compose the circuit are registered as cells in a library and layout designing is performed by citing the cells. The cells of flipflops are divided into cells of the LSSD type and cells of the MUX-D type.
A cell of a flipflop of the LSSD type includes a first selector for selecting one of a system clock and a first clock (A clock) in response to a selection signal, an invertor for inverting the system clock, a second selector for selecting one of an output signal of the invertor and a second clock (B clock) in response to the selection signal, a third selector for selecting one of a data signal and a scanning signal in response to the selection signal, a first latch circuit formed from a transmission gate or a like element for inputting an output of the fist selector as a clock and latching an output signal of the third selector at a rising edge of the clock, and a second latch circuit formed from a transmission gate or a like element for inputting an output of the second selector as a clock and latching an output of the first latch circuit.
Further, an output of the flipflop of the LSSD type is inputted as a scanning signal to another flipflop in the following stage while the system clock, A clock and B clock are inputted commonly to construct a shift register composed of a plurality of shift register, and a scanning signal is inputted from the outside to the top one of the flipflops of the shift register to form a register.
On the other hand, a cell of the MUX-D type includes an invertor for inverting a system clock in response to a selection signal, a fourth selector for selecting one of a data signal and a scanning signal in response to the selection signal, a third latch circuit formed from a transmission gate or a like element for inputting the system clock as a clock and latching an output signal of the fourth selector at a rising edge of the clock, and a fourth latch circuit formed from a transmission gate or a like element for inputting an output signal of the invertor as a clock and latching an output of the third latch circuit. Further, an output of the flipflop of the MUX-D type is inputted as a scanning signal to another flipflop in the following stage while the system clock is inputted commonly to construct a shift register composed of a plurality of flipflops, and a scanning signal is inputted from the outside to the top one of the flipflops of the shift register to form a register.
However, in a conventional semiconductor integrated circuit, a shift register is composed only of flipflops of the LSSD type or only of flipflops of the MUX-D type, but not composed of both of flipflops of the LSSD type and flipflops of the MUX-D type. Therefore, where flipflops of the LSSD type are adopted, since a test of the shift register is performed using two clocks for exclusive use which are independent of each other, that is, the A clock and the B clock, there is an advantage in that an overlap of periods of pulses of the A clock and the B clock can be eliminated with certainty, and consequently, a malfunction of any flipflop which may be caused by an overlap of periods of pulses does not occur at all and a fault of a timing error does not occur in a scanning operation. However, there is a drawback in that the circuit of flipflops is complicated by circuits of the first to third selectors and wiring lines for the three clocks and the circuit scale of the semiconductor chip becomes large.
In contrast, where flipflops of the MUX-D type are used, while there is an advantage that the circuit scale is smaller than that where flipflops of the LSSD type are used, there is a drawback that, since the system clock and the inverted system clock are used, a timing error is liable to occur in a scanning operation because of an overlap of pulses of the two clocks. As described above, in a conventional semiconductor integrated circuit for which flipflops of only one of the LSSD type and the MUX-D type are used, a scanning circuit which has a reasonable scale and is high in reliability cannot be formed.